1. Field
Exemplary embodiments of the present invention relate to an integrated circuit design technology, and more particularly, to a duty cycle correction (DCC) circuit.
2. Description of the Related Art
In integrated circuit chips that operate based on a clock (e.g. a CPU, memory device, etc), it is important to accurately control clock duty. For example, in a memory device where data is inputted/outputted at a rising edge and a falling edge of a clock, it is assumed that the duty of the clock is approximately 50%. The timing between the rising edge and the falling edge is often distorted causing data to be inputted/outputted at the incorrect time. In order to prevent this from occurring, various clock-based integrated circuit chips have a duty cycle correction circuit that corrects the duty of the clock. When the duty of a clock is 50% it means the ‘high’ level period is substantially equal to the ‘low’ level period.
FIG. 1 is a block diagram illustrating a conventional duty cycle correction circuit.
Referring to FIG. 1, the duty cycle correction circuit includes a receiver (RX) 110, a driver 120, a duty detector 130, and a duty corrector 140.
The receiver 110 receives clocks CLK and CLKB inputted to the duty cycle correction circuit. For reference, the input clock CLK_INB is a complementary clock of the input clock CLK_IN. The driver 120 drives output clocks CLK_OUT and CLK_OUTB in response to input clocks CLK_IN and CLK_INB. The duty detector 130 detects the duty of the output clocks CLK_OUT and CLK_OUTB. The duty detection consists of detecting the ‘high’ level periods and ‘low’ level periods of the output clocks CLK_OUT and CLK_OUTB. The duty corrector 140 corrects the duty of the input clocks CLK_IN and CLK_INB based on a detection result of the duty detector 130. For example, when the duty detector 130 determines that the ‘high’ level period of the output clock CLK_OUT is too long, the duty corrector 140 increases ‘low’ level period of the input clock CLK_IN, and in an opposite case, the duty corrector 140 increases ‘high’ level period of the input clock CLK_IN. Since the driver 120 employs the clocks received by the receiver 110 and a duty correction value from the duty corrector 140 as an input, the output clocks CLK_OUT and CLK_OUTB, which are duty-corrected, may be outputted from the driver 120.
The feedback-type duty cycle correction circuit as illustrated in FIG. 1 increases or decreases ‘high’ pulse widths of the input clocks CLK_IN and CLK_INB incrimentally using a feedback detection result, and is locked when the degree of distortion of the duty is reduced below a predetermined margin. That is, the duty cycle correction circuit operates similarly to a delay locked loop (DLL), and requires a separate locking time until the duty is corrected, similarly to the delay locked loop.
When a locking time is required before the duty is corrected, a device having a repeated idle mode and an active mode needs to wait for the locking time to correct the duty (the device needs to wake-up). Then, the operation mode of the device is changed from idle mode to active mode.